For Logic World players, this is a guide about simple Flip-Flops and Latches, I wll explain them with picture below, let’s check them out.
SR latches take two inputs and give one output based on input combination as following:
*X – forbidden state
JK latches also take two inputs and give one output based on input combination as following:
As seen, JK latch has an additional signal CP or CLK (Clock) which controls how often inputs affect the latch. Easiest way to make a clock is to connect output of a delayer to input of inverter and vice versa. Any node can be used as an output. Notice that frequency can be changed by editing the delayer.
T latches take one input and give one output based on input combination as following:
Notice the diagram has a clock, but I haven’t used it because I added the delayers inside the circuit.